Regviz

Freescale Semiconductor /MKE14Z7 /SCG /FIRCCSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FIRCCSR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MKE14Z7/SCG/FIRCCSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FIRCEN 0 (0)FIRCSTEN 0 (0)FIRCLPEN 0 (0)FIRCREGOFF 0 (0)FIRCTREN 0 (0)FIRCTRUP 0 (0)LK 0 (0)FIRCVLD 0 (0)FIRCSEL 0 (0)FIRCERR

FIRCLPEN=0, FIRCTREN=0, FIRCSTEN=0, LK=0, FIRCEN=0, FIRCERR=0, FIRCSEL=0, FIRCREGOFF=0, FIRCVLD=0, FIRCTRUP=0

Description

Fast IRC Control Status Register

Fields

FIRCEN

Fast IRC Enable

0 (0): Fast IRC is disabled

1 (1): Fast IRC is enabled
FIRCSTEN

Fast IRC Stop Enable

0 (0): Fast IRC is disabled in Stop modes. When selected as the reference clock to the System PLL and if the System PLL is enabled in STOP mode, the Fast IRC will stay enabled even if FIRCSTEN=0.

1 (1): Fast IRC is enabled in Stop modes
FIRCLPEN

Fast IRC Low Power Enable

0 (0): Fast IRC is disabled in VLP modes

1 (1): Fast IRC is enabled in VLP modes
FIRCREGOFF

Fast IRC Regulator Enable

0 (0): Fast IRC Regulator is enabled.

1 (1): Fast IRC Regulator is disabled.
FIRCTREN

Fast IRC Trim Enable

0 (0): Disable trimming Fast IRC to an external clock source

1 (1): Enable trimming Fast IRC to an external clock source
FIRCTRUP

Fast IRC Trim Update

0 (0): Disable Fast IRC trimming updates

1 (1): Enable Fast IRC trimming updates
LK

Lock Register

0 (0): Control Status Register can be written.

1 (1): Control Status Register cannot be written.
FIRCVLD

Fast IRC Valid status

0 (0): Fast IRC is not enabled or clock is not valid

1 (1): Fast IRC is enabled and output clock is valid
FIRCSEL

Fast IRC Selected status

0 (0): Fast IRC is not the system clock source

1 (1): Fast IRC is the system clock source
FIRCERR

Fast IRC Clock Error

0 (0): Error not detected with the Fast IRC trimming.

1 (1): Error detected with the Fast IRC trimming.

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data